| Paper: | DISPS-L2.3 |
| Session: | Algorithm and Architecture Co-optimization |
| Location: | Syndicate 4 |
| Session Time: | Tuesday, May 14, 17:30 - 19:30 |
| Presentation Time: | Tuesday, May 14, 18:10 - 18:30 |
| Presentation: |
Lecture
|
| Topic: |
Design and Implementation of Signal Processing Systems: Programmable and reconfigurable DSP architectures |
| Paper Title: |
LOW-POWER PROGRAMMABLE PROCESSOR FOR FAST FOURIER TRANSFORM BASED ON TRANSPORT TRIGGERED ARCHITECTURE |
| Manuscript Link: |
Click here to view manuscript on IEEE Xplore |
| Authors: |
Jakub Žádník, Jarmo Takala, Tampere University, Finland |